The full form of PCI is Peripheral Component Interconnect. It is
basically a computer expansion card standard which describes the the
computer bus architectures to connect components on the computer
motherboard and also to provide an expansion interface to plug in add on
cards. The team which standardized the PCI bus architecture is known as
PCI Special Interest Group or PCISIG in short form. PCISIG is a group
of more than 900 companies, which has been designing and developing
enhanced versions of PCI standards to meet the growing requirements of
high performance computer bus system. The PCI standards define a full
plug and play capability which enables the computer Basic Input and
Output System(BIOS) and the operating system to determine the resource
requirements, such as interrupts, I/Os and memory and assign resources
in such a way so that the conflict with other devices could be avoided.
Brief History
PCI Express standards represent the third generation of IO technology. Industry Standard Architecture or ISA was the first generation of IO technology, designed and developed by IBM in 1981. Then came PCI, the second generation IO technology which was created by Intel in 1993. Finally, to meet the growing need of bandwidth, Intel invented PCI Express in 2004. Though initially, it was designed to facilitate high speed audio and video streaming, but in the later stages, PCI Express became an important tool to improve the data communication between the measurement instruments and computer by a margin of 30 times, compared to conventional PCI bus.
PCI Express Architecture
PCI Express was developed to enhance the performance of old PCI standards, which used a clock of 33 MHz and transmitted 32 bits with the maximum bandwidth of 132 Mbits/second. The earlier version of PCI bus employed shared bus topology, in which bus bandwidth was divided by multiple devices to enable communication among them. Later on, new devices emerged which required more bandwidth resulting in bandwidth reduction. To overcome this limitation, PCI Express standard was created, which uses point to point bus topology. The shared bus used for PCI is substituted with a shared switch, which provides bus access to each device. Instead of dividing the bandwidth among devices connected to the bus as the older PCI versions did, the PCI Express provides dedicated data pipeline to each device. Data is transmitted and received serially in packets through pairs of transmit and receive wires, known as lanes. Thus the PCI Express architecture supports full duplex communication between two devices with no restriction on concurrent access across multiple devices. The transaction layer of the PCIe port handles the message traffic.The maximum communication speed is 250 Mbits/second.
The PCIe connection between two devices could comprise maximum of 32 lanes. The number of lanes is automatically determined during the initialization of devices and could be restricted by either of the devices. The PCIe standard specifies slots and connectors for multiple link widths. This enables the PCIe bus to cater to both performance critical applications as well as cost sensitive applications.
Compatibility Of PCIe With Older Versions Of PCI
Though PCIe maintains backward compatibility with older versions of PCI at the software level, but substitutes the physical layer with a high speed serial bus of 2.5Gigabites/second. That is why PCIe and PCI slots are not compatible. Devices with smaller connectors could be plugged into bigger host connectors on the motherboard but devices with larger connectors cannot be plugged into devices with smaller connectors.
PC Support For PCI Express
PCIe bus is widely used in numerous industrial, server and consumer applications. Its is mainly used as an expansion card interface for add-on boards as well as motherboard interface. In almost all types of computers, PCIs bus operates as the basic motherboard interface, connecting the host system processor to the on-board and add-on peripherals. So if PCIe bus goes bad, then the entire computer system might start malfunctioning. Since the PCIe bus technology is a complex one, Network Support for it should be availed of. Nowadays many Computer support providers are rendering tech support for PCIe bus technology.
Brief History
PCI Express standards represent the third generation of IO technology. Industry Standard Architecture or ISA was the first generation of IO technology, designed and developed by IBM in 1981. Then came PCI, the second generation IO technology which was created by Intel in 1993. Finally, to meet the growing need of bandwidth, Intel invented PCI Express in 2004. Though initially, it was designed to facilitate high speed audio and video streaming, but in the later stages, PCI Express became an important tool to improve the data communication between the measurement instruments and computer by a margin of 30 times, compared to conventional PCI bus.
PCI Express Architecture
PCI Express was developed to enhance the performance of old PCI standards, which used a clock of 33 MHz and transmitted 32 bits with the maximum bandwidth of 132 Mbits/second. The earlier version of PCI bus employed shared bus topology, in which bus bandwidth was divided by multiple devices to enable communication among them. Later on, new devices emerged which required more bandwidth resulting in bandwidth reduction. To overcome this limitation, PCI Express standard was created, which uses point to point bus topology. The shared bus used for PCI is substituted with a shared switch, which provides bus access to each device. Instead of dividing the bandwidth among devices connected to the bus as the older PCI versions did, the PCI Express provides dedicated data pipeline to each device. Data is transmitted and received serially in packets through pairs of transmit and receive wires, known as lanes. Thus the PCI Express architecture supports full duplex communication between two devices with no restriction on concurrent access across multiple devices. The transaction layer of the PCIe port handles the message traffic.The maximum communication speed is 250 Mbits/second.
The PCIe connection between two devices could comprise maximum of 32 lanes. The number of lanes is automatically determined during the initialization of devices and could be restricted by either of the devices. The PCIe standard specifies slots and connectors for multiple link widths. This enables the PCIe bus to cater to both performance critical applications as well as cost sensitive applications.
Compatibility Of PCIe With Older Versions Of PCI
Though PCIe maintains backward compatibility with older versions of PCI at the software level, but substitutes the physical layer with a high speed serial bus of 2.5Gigabites/second. That is why PCIe and PCI slots are not compatible. Devices with smaller connectors could be plugged into bigger host connectors on the motherboard but devices with larger connectors cannot be plugged into devices with smaller connectors.
PC Support For PCI Express
PCIe bus is widely used in numerous industrial, server and consumer applications. Its is mainly used as an expansion card interface for add-on boards as well as motherboard interface. In almost all types of computers, PCIs bus operates as the basic motherboard interface, connecting the host system processor to the on-board and add-on peripherals. So if PCIe bus goes bad, then the entire computer system might start malfunctioning. Since the PCIe bus technology is a complex one, Network Support for it should be availed of. Nowadays many Computer support providers are rendering tech support for PCIe bus technology.
Christie Hemme is one of most heralded content writer of pccarencure.com. Pccarencure offers 24x7 Computer Support, Network Support, PC Support, IT Support, to millions of customers, via Remote Computer Support, from expert technicians.
Article Source:
http://EzineArticles.com/?expert=Christie_Hemme
0 komentar:
Posting Komentar