PCI Special Interest Group (PCI-SIG) As with AGP & PCI, the development of PCI Express can be attributed to Intel. This time, however, they partnered with some other heavy hitters in the industry, such as Microsoft, IBM, & Dell. Although it is now known as PCI Express, that was not their preliminary choice for its name. If it wasn't for PCI-SIG, the committee that oversees the PCI standard, they might be referring to this new format at 3GIO (Third Generation Input / Output).
PCI Express development finds its roots in the PCI & AGP standards, but the physical connections are not interchangeable, & they will see that this is not the only difference. In the PCI standard, knowledge from the various devices travels over a shared bus to the technique. In the AGP standard, a dedicated, point-to-point interface transmits the knowledge from the graphics card to the technique. The PCI Express approach to knowledge transfer involves a collection of two-way, serial connections that carries knowledge in packets, similar to the way a network connection operates.
The knowledge from a PCI Express device will no longer must travel over a single bus, or a single dedicated connection, but can use a combination of these two-way serial connections to optimize throughput. The terms "lane" & "link" don't sound like anything excessively technical, but take on special meaning with PCI Express. A link is the physical connection between PCI Express devices, which can consist of multiple lanes that transmit & get knowledge independently. Links can be composed of, 8, 12, 16, or 32 lanes, & the configuration allows flexibility in assigning as lots of lanes as needed to any particular device. There are obvious benefits to this approach, & some of the more significant include the following points...
Each lane of PCI Express communication is dedicated between points, so there is no sharing of bandwidth. PCI's main bottleneck was that all the devices were sharing the equivalent of lane, & all of the available bandwidth also had to be shared.
Multiple lanes can be assigned to devices whose performance would benefit from the additional speed & bandwidth. A PCI Express graphics card might be assigned 16 lanes (often known as x16), while a network adaptor might be assigned lane. Each lane you make available to a device increases the potential for performance, as the knowledge is sequenced up/down each available lane to optimize throughput. This technique of sending the next byte of knowledge down the next available lane is named knowledge striping, & obviously more lanes are better for instances where a great deal of knowledge needs to be transmitted quickly.
Speaking of graphics cards, another benefit is that multiple high performance graphics cards can be installed on motherboard. The flexibility of PCI Express allows for x16 PCI Express slots to be included for dual graphics cards, something that historically in the past necessary AGP slot & PCI slot. & due to the performance limitations, the AGP & PCI combination could not be thought about high performance. In addition to x16 slots allowing for dual display operation, when incorporating specific graphics cards on a motherboard supporting NVidia’s SLi know-how, the resources of the separate cards can be bridged together for even greater performance on display. An example of such a motherboard can be seen in DFI's LAN Party UT nF4 SLi-D.
(to be continued...)
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